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Digital SWM theory and speculation


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#21 OFFLINE   Stuart Sweet

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Posted 24 December 2013 - 09:33 PM

Seems to me that I read where around 98% of customers are satisfied with 8 tuners or fewer. Granted that does leave roughly 400,000 households that want more than 8, but it certainly makes one wonder how it would be possible to achieve economies of scale for a new SWM with more than 16 tuner capacity unless it was required for future technologies.

It's clear that it's just been in the last 18 months or so that SWM16s have become inexpensive when purchased through legitimate sources, implying that it took 3ish years to make up the R&D investment. Putting aside the specific design of the DSWM13 which exists for a specific market, it's hard to see the economics of a future DSWM product being cost competitive with the existing ASWM devices. Unless, as I said, the existing SWM is somehow incompatible with future broadcasting.
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#22 OFFLINE   slice1900

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Posted 25 December 2013 - 01:33 AM

Based on that 98% figure, it would have to come down to DSWM being cheaper than analog SWM and entirely replacing it, because the volumes for SWM16 replacement would be too small. That's clearly a higher bar, but I don't believe it is as hopeless you feel it is. It will all come down to the cost per unit to make the DSWM ASIC, the NRE costs will become insignificant if it replaces the ASWM entirely. The ASWM contains a number of discrete components, including 9 SAWs and 3 RF5200 (or similar) chips, along with a 6x9 multiswitch at the input, all of which would be replaced by the DSWM ASIC.

 

The big unknown is the size of that ASIC. I understand the scale of it, but i don't really know what the computational requirements for each transponder are to implement the filtering, and the wiring for a mux able to handle up to 264 inputs (one per transponder) won't be pretty and could require a couple additional metal layers on its own.

 

For a foundry pricing comparison, its estimated Apple pays about $20 for the 100 sq mm A7 SoC in the latest iPhone & iPad. That's the price to have them made from Apple's "blueprints", including foundry profit, exclusive of Apple's NRE costs. Directv wouldn't buy DSWM ASICs at volumes remotely close to Apple, but the good news for them is that the economies of scale for a foundry peter out at around 1000 wafers (let's call that a half million A7 sized chips) so they don't need to buy in the tens of millions quantities Apple does to get similar pricing. I wonder how many SWM8, SWM16, and SWM LNBs are made in a year? A couple million, maybe? They should easily reach the thousand wafer bar - if they don't it means the DSWM ASIC is tiny, and they've already won.

 

A production volume of several million over a two year period drops the cost of the $3 million mask set to around $1/unit. The design costs of the ASIC itself are largely a sunk cost by virtue of the existence of the DSWM13, but they'd still need to design a DSWM LNB and an external DSWM module, provide installer training, etc. so maybe a $5 more per unit to account for all that, but largely amortized after the first year or so.

 

If the DSWM ASIC is around the size of Apple's A7, the $25/chip cost would compare unfavorably with ASWM, based on the Ebay pricing for SWM8s and SWM LNBs. If its half that size, at $15/chip, it may be close, especially in the second year when it is around $11/ea. A quarter the size and I think we have a winner! If the DSWM ASIC in the DSWM13, implemented in 45nm CMOS, is 100 sq mm, then implemented in 20nm CMOS it would be a quarter that size, and TSMC could start to deliver 20nm chips by next summer. If its larger, they need to wait a couple years for a smaller process, or value other advantages of DSWM - i.e. the frequency drift control and installation/diagnostic support mentioned in the other patent reducing their support costs.

 

Wish there was a way to find out the size of the ASIC in the DSWM13 - but even if someone had one to experiment on the chip would have to be desoldered and delidded to see the actual size, since the package you can see when you look at a board is governed by pin spacing and the size of the pad, not the often much smaller silicon chip inside.


SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21


#23 OFFLINE   slice1900

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Posted 25 December 2013 - 01:58 AM

Thinking more about the second patent, how much value would there be for Directv from a "smarter" LNB? Controlling frequency drift is nice, assuming temperature or aged related drift is a common reason LNBs have to be replaced for intermittent type issues, so replacements can be reduced.

 

Having the LNB able to tell a receiver when the drift risks getting too large to compensate for makes it even better. The receiver could either report it to Directv via the internet or tell the customer to call them. That's a lot nicer than people having intermittent problems they don't understand, and eventually calling Directv and trying to explain them, or coming to dbstalk for help. Or getting frustrated thinking those types of occasional problems are normal and going back to cable after the two years are up.

 

I also wonder, could the LNB tell the installer what to do to adjust the aim (once there's at least a little signal coming in) and tell the installer when they've got it aimed just right? The installer wouldn't look at a signal beyond getting something coming in, then he'd start receiving instructions to adjust this, then adjust that, monitoring the results of each step he performs and telling him the next step until he's done and the process could be made pretty foolproof. Much nicer for customers trying to aim dishes at a tailgate if the receiver could provide those instructions!

 

If these things could be done, how much is that worth to Directv in reduced support/installation/retention costs?


SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21


#24 OFFLINE   P Smith

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Posted 25 December 2013 - 10:54 AM

could require a couple additional metal layers on its own.

 

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#25 OFFLINE   slice1900

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Posted 25 December 2013 - 02:23 PM

[voice from crowd]

metal [practically a copper] layers are for PCB, not in chips; there is more Si then Me

[/voice from crowd]

 

Not so, all silicon chips have multiple metal layers, which are deposited using CVD or similar one on top of the other, with an insulating layer deposited between them, then holes "cut" and filled in the dialectric for vias where the metal layers require connection. Transistors are formed on the very bottom, directly on the silicon wafer surface. Signal routing wires go in the layers above the transistors, short wires on the bottom and long (thicker) wires above, then one or more power planes form the top of the stack with the thickest metal. How do you think power and communication happen between all those isolated transistors deposited in the initial steps, if there are no wires? :)

 

These days very complex chips can have quite a few metal layers, for instance Intel currently uses nine in making their CPUs. The number of metal layers used in complex chips keeps going up and up as the transistors get smaller, because wires can't get smaller at the same rate so you either waste area not spacing your transistors as closely as you could, or you make the metal stack taller. Back in the days of the Apple II they could get away with only one or two metal layers in the tiny CPUs of the day, because the transistors were so big.

 

Simple stuff like DRAM and FPGAs has only three layers these days, and the DSWM ASIC, since it is mostly a DSP, is of comparable complexity, but that big multiplexer would need one layer to avoid wasting area. I was thinking perhaps two in my previous post, as typically you want to avoid the long wires that would result from the inefficient routing trying to cram that in a single layer. However the reasons you don't want long wires (propagation delay that scales roughly in proportion to the wire length squared, and resistive power losses) don't really matter in this case.

 

Additional metal layers increase wafer processing time and therefore cost, so I guess that's an advantage for the DSWM ASIC compared to the A7 I didn't think about previously. I have no idea how many metal layers the A7 uses, Apple is even more secretive about its tech than Directv, but it is safe to assume the number is closer to Intel's nine than a DSP's three. I don't know exactly much you save using half the metal layers of a chip of equivalent size, but it should knock down the DSWM ASIC cost a bit in my previous post.

 

Here's an image from a scanning electron microscope of what the metal stack actually looks like, with the metal layers labeled M1 through M6:

 

fig1.large.gif


SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21


#26 OFFLINE   HoTat2

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Posted 25 December 2013 - 02:57 PM

Based on that 98% figure, it would have to come down to DSWM being cheaper than analog SWM and entirely replacing it, because the volumes for SWM16 replacement would be too small. That's clearly a higher bar, but I don't believe it is as hopeless you feel it is. It will all come down to the cost per unit to make the DSWM ASIC, the NRE costs will become insignificant if it replaces the ASWM entirely. The ASWM contains a number of discrete components, including 9 SAWs and 3 RF5200 (or similar) chips, along with a 6x9 multiswitch at the input, all of which would be replaced by the DSWM ASIC.

 

The big unknown is the size of that ASIC. I understand the scale of it, but i don't really know what the computational requirements for each transponder are to implement the filtering, and the wiring for a mux able to handle up to 264 inputs (one per transponder) won't be pretty and could require a couple additional metal layers on its own. ...

 

 

Just a couple of questions here;

 

1) Where does an internal 6x9 multiswitch fit into the picture of the ASWM?

 

From the ASWM schematic in the patent in Fig. 2 its looks as there are just 4 inputs issuing from the LNB module illustrated in Fig. 3A.

 

The two Sat A inputs are fed to one RF5200 chip as well as branched off to feed the two other RF5200 chips effectively in parallel with the first. And likewise the two inputs from 119 and 110/119 (i.e. Sat B and B+C) are fed to one RF5200 chip as well as branching off to feed the two others in parallel. Thus each RF chip has 4 inputs for a total of 12 combined.

 

2) I've counted and recounted, and I can't see why 264 inputs (at 1 per transponder) to the DSWM internal mux. are necessary.  

 

For an SL-5 for instance, with the current transponder assignments and channelization schema, the 99 slot = 48 tps. max, 101 = 32, 103 = 48 max. 110 = 3, and 119 = 11, totals only 142. Even adding prospective RDBS band only adds 36 more transponders for a total of only 178.  :confused:   


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#27 OFFLINE   P Smith

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Posted 25 December 2013 - 04:28 PM

[chip's layers]

Umm, OK, if it metal layer, then it would more interconnection planes then a "layer"

I'm aware of MDP stage of wafer's processing and many more ...

[/chip's layers]



#28 OFFLINE   slice1900

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Posted 25 December 2013 - 08:28 PM

Just a couple of questions here;

 

1) Where does an internal 6x9 multiswitch fit into the picture of the ASWM?

 

From the ASWM schematic in the patent in Fig. 2 its looks as there are just 4 inputs issuing from the LNB module illustrated in Fig. 3A.

 

The two Sat A inputs are fed to one RF5200 chip as well as branched off to feed the two other RF5200 chips effectively in parallel with the first. And likewise the two inputs from 119 and 110/119 (i.e. Sat B and B+C) are fed to one RF5200 chip as well as branching off to feed the two others in parallel. Thus each RF chip has 4 inputs for a total of 12 combined.

 

2) I've counted and recounted, and I can't see why 264 inputs (at 1 per transponder) to the DSWM internal mux. are necessary.  

 

For an SL-5 for instance, with the current transponder assignments and channelization schema, the 99 slot = 48 tps. max, 101 = 32, 103 = 48 max. 110 = 3, and 119 = 11, totals only 142. Even adding prospective RDBS band only adds 36 more transponders for a total of only 178.  :confused:   

 

 

There is no multiswitch shown in the drawing, I'm assuming it is covered under the "routing of LNA signals to all three chips" label on Figure 2. If there's no multiswitch, each SWM chip would require six inputs to be able to select any possible channel on its three outputs. The only FDM chips on Entropic's site that aren't designed for the FTA market, the RF5200/RF5201, have two or three inputs, as opposed to the four inputs shown in the drawing. As with the flex ports, some detail has been omitted. We're left to fill in the blanks with what we know (ASWM supports flex ports) and with guesses for what we don't (there must be some sort of multiswitch, or there are six inputs to each chip)

 

The analog SWM patents, which quite accurately describes today's SWM (along with other embodiments & details that were not implemented) also show and mention a multiswitch at the front end. Of course, the drawing in those patents shows an 8x8 multiswitch, but with nine outputs coming from the FTM! There's always some things that make you scratch your head and leave it up to the reader to fill in the gaps...

 

I said up to 264 transponders, but there aren't that many today. The four outputs of a SL3/SL5 each stack 2 Ka bands (24 tpns) and one Ku band (16 tpns) for a total of 40. I guess I did the math backwards and got 16+16+12 for 44, oops :) Not all the transponders on 110/119 are active, but you have to do the design to support them all unless you assume that slot will always be used for 110/119 and there will never be more tpns added there.

 

So far, 4*40 = 160, then there are the two flex ports. If they're truly flexible, they'll support 40 more themselves based on a similar stack plan. 6*40 = 240. Who knows, if they anticipate ever possibly having a Ku band arrive in 250-750 or 1650-2150, they might support the possibility of as many as 48 transponders per LNB, or 288 total.

 

They could make the mux simpler if it only supports what they have today and what they know they'll have in the immediate future, but the flexibility of the DSWM is wasted if they limit it to save pennies by cutting it down to the minimum needed. They can still limit it via software, so it won't attempt to digitize the unused bands/transponders and the mux can ignore those inputs. That'll save a bit of power.


Edited by slice1900, 26 December 2013 - 04:01 AM.

SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21


#29 OFFLINE   slice1900

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Posted 25 December 2013 - 09:13 PM

[chip's layers]

Umm, OK, if it metal layer, then it would more interconnection planes then a "layer"

I'm aware of MDP stage of wafer's processing and many more ...

[/chip's layers]

 

 

OK, keep in mind I'm not an EE, the closest I've come to actually doing this is playing around with Mentor Graphics and Cadence tools when I worked an electronics company. That said, I don't see why you'd need more than a single plane for this. There is no "order" to which tpn has to go to which input of the mux, they're all equivalent. Just because the mux is shown in the drawing with the inputs on the left doesn't mean it wouldn't be entirely ringed with inputs. You'd almost have to do that, since its size would be dominated by the number of vias it has to support.

 

On the "mux metal layer", you only need to find an unbroken point to point route between each output (labeled 506 in Figure 5) to the input of the mux. You have the entire chip area in which to do so, so you could make some pretty circuitous paths if necessary. If you had to pop down to a lower layer in a few places where paths just had to cross that shouldn't be too much of a problem. The place and route software was already pretty good at this sort of thing when I was toying around, and it has undoubtedly advanced a hell of a lot since. I doubt the guys doing this ASIC would be doing much hand routing, that's typically reserved for speed critical stuff.


SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21


#30 OFFLINE   slice1900

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Posted 28 December 2013 - 04:11 PM

I managed to obtain some additional information about the DSWM ASIC. Unfortunately I cannot reproduce it, but I learned some interesting things.

 

The DSWM ASIC implemented in 45nm CMOS uses 7 metal layers and I'd estimate the die size at a bit over 30 sq mm (based on holding a ruler up to a die photo that identified a few functional blocks and the sizes of those functional blocks identified elsewhere) If produced in sufficient quantity, I'd guess it should cost under $10/ea. This is more metal layers than I expected, but this is a mixed signal ASIC and I suppose I should have realized this will add additional layers. It uses RDL packaging, which is a cost saving measure made possible by the small number of I/Os.

 

The ASIC has only 14 input bands (same as SL5 + 72.5/95) not the 18 I was guessing to allow for truly flexible flex ports. All are input to the ASIC on B band (250 to 760 MHz) Only 14 bands is rather surprising given that one of the stated goals of the DSWM in both the patent and the paper was flexibility to increase the number of inputs/satellites. Assuming 14 inputs is accurate (i.e. not a "fib" to avoid tipping their hand for future plans) it puts some limits on what Directv's future plans are, if any, for customer content delivered from RDBS/BSS. That is, if they add it from 99 and/or 103, they would have to replicate channels from and drop 119 and/or 95.

 

Based on the block diagrams and additional description, the DSWM ASIC implements the second embodiment from the patent, not the first. There are 24 output channels, making a DSWM23 module possible. The channel width isn't provided but VOS already said they were "half the size", and it looks to be just under that (<=50 MHz rather than 51 MHz) I have output from a spectrum analyzer showing the 24 channels, but unfortunately it is a poor reproduction and it isn't possible to read the scales on either axis.

 

The ASIC monitors temperature, so it can presumably shut down or put up alerts on the receivers or something if it gets too hot. The power consumption for the entire ASIC, with all 14 DSP "slices" active is 9.4 watts, but if certain input bands are not used (i.e. have no channel from them selected) the DSP slices dedicated to them are deactivated to reduce power consumption. The 9.4 watts does not include whatever else a DSWM module may need, though external components shown are mostly passive devices.

 

The figure of 9.4 watts doesn't seem to match what Stuart was suggesting about the DSWM13's power consumption, though we should find out actual numbers fairly soon for a better comparison. If accurate, it is only a couple watts more than a SWM8, which seems to be fine for inclusion in a LNB.


Edited by slice1900, 28 December 2013 - 04:13 PM.

SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21


#31 OFFLINE   P Smith

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Posted 28 December 2013 - 05:57 PM

Unfortunately I cannot reproduce it

perhaps we could follow you if there is an URL ?



#32 OFFLINE   HoTat2

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Posted 29 December 2013 - 11:47 AM

So to summarize your latest findings on the DSWM ASIC;

 

1) Only 14 band inputs, where 12 alone of those would be needed for a SL-5?

 

2) All bands are converted to the Ka-lo range of 250-750 MHz to feed the ADCs instead of a starting frequency in 10-100 MHz range as suggested in the patent?

 

3) Up to 24 possible outputs, but only 13 activated in the present implementation?

 

I must say I'm underwhelmed and sort of confused by the specification choices from the manufacturer if accurate.    


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#33 OFFLINE   P Smith

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Posted 29 December 2013 - 12:46 PM

that's why I'd like to explore original documents...



#34 OFFLINE   inkahauts

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Posted 29 December 2013 - 01:32 PM

Don't forget everything does need to come back to working with decas limit or 13 nodes for this particular need and distance requirements. Also If they used lower channels would it not interfere with deca? And the way vos has talked about it, I don't even think using moca2 with twice the bandwidth would allow more nodes because the issue is distance and signal amplification more than number of nodes that can be active at one time for this implementation.

#35 OFFLINE   slice1900

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Posted 29 December 2013 - 02:57 PM

I had a friend who works for a company with a corporate IEEE membership obtain the ISSCC paper and some slides and Q&As from the presentation, but I can't reproduce them here or make them available on the web. Apparently they encode something on all downloads that links back to the downloader to prevent redistribution. He was pretty adamant that he would only give them to me if I promised I wouldn't share them with anyone, because he could get in a lot of trouble at work even for sharing this material with me, I'm sorry. I can answer questions however.

 

Most of the detail was about circuit level specifics, like using the time delay inside the ADC circuit to generate an extra bit of resolution, the noise factors through different parts of the circuit, etc.

 

 

1) Only 14 band inputs, where 12 alone of those would be needed for a SL-5?

 

Yes, I found that rather surprising as well. Unless Directv's engineers told NXP to claim there were only 14 bands / DSP slices to hide their future intentions/capabilities, it puts some boundaries on what they can do with RDBS without duplicating and dumping other stuff. Also limits speculation about Directv someday changing how to they uplink locals to allow Ka from 101 to be converted to customer broadcast, or applying for Ku from 99 and 103 if/when the FCC approves 2* Ku spacing.

 

 

2) All bands are converted to the Ka-lo range of 250-750 MHz to feed the ADCs instead of a starting frequency in 10-100 MHz range as suggested in the patent?

 

Yes, the bands are input to the ASIC at a slightly higher range than in the patent. The high end 760 MHz was specifically provided in several places, so I don't believe that was an error. I have seen mention of converting Ku to 250 - 750 MHz and both Ka bands to 260 - 760 MHz in several LNB related patents, if they're doing it elsewhere (such as in a SWM LNB) they may have wanted to re-use the same front end.

 

 

3) Up to 24 possible outputs, but only 13 activated in the present implementation?

 

The DSWM13 could never have supported more than 15 channels due to DECA limitations, but per VOS the DECA losses were a problem so they had to design it for only 13. In the DSWM13, the ASIC would presumably be programmed to limit itself to 13 channels - there's a flash interface on the DSWM ASIC designed to use an external flash module. There is no mention of exactly what is stored there, or how programmable it is.

 

 

Don't forget everything does need to come back to working with decas limit or 13 nodes for this particular need and distance requirements. Also If they used lower channels would it not interfere with deca? And the way vos has talked about it, I don't even think using moca2 with twice the bandwidth would allow more nodes because the issue is distance and signal amplification more than number of nodes that can be active at one time for this implementation.

 

FWIW, MoCA 2.0 retains the same 16 node limit, so even if Directv upgraded for more speed it won't change that limit. Presumably a DSWM23 wouldn't be a problem, since MoCA is primarily intended for MRV, and you'd have to be very receiver/client heavy to run into problems.

 

If I upgraded all my H20s to H24s and wanted to network them all I'd be restricted to putting 15 on a DSWM23, though I could always feed the output into a two way splitter and put a diplexer/DECA on each leg if I wanted to use the full 23 channels. I'd probably need multiple layers of splitters anyway as I don't foresee a SWS-24 offered anytime soon :)


SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21


#36 OFFLINE   inkahauts

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Posted 29 December 2013 - 04:41 PM

Sounds like the 24 Dswim would be pointed at mdu since you can and have to put a bsf for each unit in place to keep everyone's system self contained and create a deca cloud for every unit. So the next question will be how much will a Dswim 24 be over a swim32?

#37 OFFLINE   slice1900

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Posted 30 December 2013 - 03:07 AM

Sounds like the 24 Dswim would be pointed at mdu since you can and have to put a bsf for each unit in place to keep everyone's system self contained and create a deca cloud for every unit. So the next question will be how much will a Dswim 24 be over a swim32?

 

So long as they make a DSWM LNB, a DSWM23 module would be almost exclusively a commercial/MDU product. As such, it probably would have more than two outputs. That would allow them to maintain the output at the current ~ -30 dbm AGC level, along with the same splitter/distance guidelines, and avoid the need for a BSF :) This would be very nice for the MDU market, since say four units sharing 23 channels is a more flexible solution that I'd guess probably works out more often than four units each getting exactly 8 channels as with a SWM32 or SWM8 based solution.

 

Based on the ASIC's die size, and that it doesn't appear there's anything that costs much in a DSWM module beyond the ASIC, I think the cost of production for a DSWM23 and a SWM8 would be very much in the same ballpark, if produced in similar quantities. While I believe this bodes well for a DSWM LNB, the existence of a DSWM LNB would mean quite a bit fewer DSWM23s would be produced compared to SWM8s/SWM16s. Worse yet for the DSWM23 price, Directv would almost have to keep selling SWM8s for some time, since there is MDU gear designed for them. While I don't think the price for a DSWM23 would be as bad as the red headed stepchild that is the SWM32, they definitely won't be on Ebay for $50 like SWM8/SWM16s, either!

 

I will say, given how small the die already is, and the rather modest power consumption indicated, there doesn't seem to be any real need to shrink it further. Mass production in 45nm would be a reasonable decision, unless there was something beyond rather minor fixes/enhancements they needed/wanted to do. In that case, shrinking to 32nm/28nm as part of the redesign probably makes sense.


SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21


#38 OFFLINE   slice1900

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Posted 31 December 2013 - 12:59 AM

I made a few updates to my post #2, to include details learned from the paper other materials I received and where it differs from or clarifies the patent description. I added a link to an Entropic patent application filed August 2012 for a Directv LNB that uses a single LO with frequency divisors to receive Ku from 101, Ka lo/hi from 99/103, and RDBS/BSS from 103. The main reason I added it was because it describes and implements a requirement for output of individual bands in the 250 - 760 MHz range. Not saying that is what a DSWM LNB would look like, but I felt it was "interesting" enough to include in light of the match with the input range expected by the DSWM ASIC. However, the prior art indicates a similar input frequency range is used in the analog SWM LNB, so a DSWM LNB could presumably use the same front end as a SWM LNB (likewise a new model of analog SWM LNB could use the front end from this patent)

 

One detail I missed on initial reading of the paper relevant to the last few posts. The patent states the DSWM would shift the frequency to "near baseband" before digitization (the exact wording was "tunable starting frequency from 10 to 100 MHZ, or beyond these limits if desired.") The paper states the ASIC expects an input in the B band (250 - 760 MHz) but that after digitization it is shifted to a frequency "centered around 0", i.e. -250 to +250 MHz. The 24 output channels are similarly generated at -600 to +600 MHz, before being shifted to L band (950 - 2150 MHz) prior to passing through the DAC at the output.


Edited by slice1900, 31 December 2013 - 01:00 AM.

SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21


#39 OFFLINE   inkahauts

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Posted 31 December 2013 - 04:34 PM

So long as they make a DSWM LNB, a DSWM23 module would be almost exclusively a commercial/MDU product. As such, it probably would have more than two outputs. That would allow them to maintain the output at the current ~ -30 dbm AGC level, along with the same splitter/distance guidelines, and avoid the need for a BSF :) This would be very nice for the MDU market, since say four units sharing 23 channels is a more flexible solution that I'd guess probably works out more often than four units each getting exactly 8 channels as with a SWM32 or SWM8 based solution.

Based on the ASIC's die size, and that it doesn't appear there's anything that costs much in a DSWM module beyond the ASIC, I think the cost of production for a DSWM23 and a SWM8 would be very much in the same ballpark, if produced in similar quantities. While I believe this bodes well for a DSWM LNB, the existence of a DSWM LNB would mean quite a bit fewer DSWM23s would be produced compared to SWM8s/SWM16s. Worse yet for the DSWM23 price, Directv would almost have to keep selling SWM8s for some time, since there is MDU gear designed for them. While I don't think the price for a DSWM23 would be as bad as the red headed stepchild that is the SWM32, they definitely won't be on Ebay for $50 like SWM8/SWM16s, either!

I will say, given how small the die already is, and the rather modest power consumption indicated, there doesn't seem to be any real need to shrink it further. Mass production in 45nm would be a reasonable decision, unless there was something beyond rather minor fixes/enhancements they needed/wanted to do. In that case, shrinking to 32nm/28nm as part of the redesign probably makes sense.


Wait, why are you saying they won't need a bsf in easy terms? I don't see how they couldn't. And I also don't see why they'd need more than one output unless they where just going to create a unit that was built like two dswim13 which would be far less versitale for MUDs than one dswim24 would be. I'd also expect them to make these units have a regular power output like today's sims units not the higher voltage that the dswim appears to have. You wouldn't use a tap system in an mdu.

#40 OFFLINE   slice1900

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Posted 01 January 2014 - 03:18 AM

Wait, why are you saying they won't need a bsf in easy terms? I don't see how they couldn't. And I also don't see why they'd need more than one output unless they where just going to create a unit that was built like two dswim13 which would be far less versitale for MUDs than one dswim24 would be. I'd also expect them to make these units have a regular power output like today's sims units not the higher voltage that the dswim appears to have. You wouldn't use a tap system in an mdu.

 

 

The DSWM13 was designed for a specialized market, and as such is about as applicable to the direction of future DSWM products as the H20i was to the direction of future receivers. We know how many channels the ASIC is capable of, and why the DSWM13 was limited to only 13. We know the reason why it has a high power output and uses taps rather than splitters. Neither choice would be made with a DSWM LNB targeted at the residential/light commercial market or a DSWM23 module targeted at replacing the SWM8/SWM16/SWM32 in commercial/MDU markets.

 

There is nothing in the DSWM ASIC's design that biases it towards the DSWM13's high output level. According to the paper, the DSWM ASIC includes 14 multistage AGC amps (30 db dynamic range, 20 db max gain, very similar specs to the ASWM) to level adjust each band before it's digitized, along with a digital AGC stage after the mux that individually levels the 24 channels to the desired output strength. I have no idea what limits there may be on the range of that "digital AGC amplifier". Like digital filtering, I'm sure some of the limitations of the analog RF world affect the digital equivalent, but if we assume it is merely able to manage the same specs as its 14 analog brothers, it should be capable of the DSWM13's required output level as well as the level desired from a traditional SWM output. That is, if you assume a traditional SWM outputs at -30 dbm, and a DSWM13 outputs at -10 dbm (based on clues provided by VOS) that's covered by a 20 db max gain. The extra 10 db of dynamic range covers the 10 db difference in the strongest and weakest transponders in a single band (this was mentioned in the patent)

 

You suggest a DSWM23 wouldn't "need" more than one SWM output sharing its 23 channels. So why does the SWM8 have two outputs sharing only 8 channels? Wouldn't similar reasons for that decision apply to a DSWM23, only moreso considering it would have nearly 3x the channels? Having an internal splitter can't cost much, or the SWM8 would have just one output. Multiple outputs would allow each to have the same ~ -30 dbm output as today's SWM ports do, therefore having the same splitter/length recommendations. That makes training/support easier, as there wouldn't be a separate set of guidelines for the DSWM module.

 

I believe it also makes sense for a DSWM23 module to block DECA from passing between those multiple outputs. First, because without BSFs it would exceed the 16 node limit in some commercial use cases. Second, the DECA loss budget would be significantly impacted if there were 8 way splitters used on the outputs (i.e. > 4 receivers/DVRs on at least two of those outputs) in addition to the 4 way internal splitter. Third, it avoids the need for a BSF pigtail on each output in MDU environments. Fourth, I just can't think of any use cases where you must use multiple outputs and must pass DECA between them. On the other hand, Directv would have to add something to filter DECA, so maybe they leave it out to save a few pennies and figure BSFs will be used where needed, since that's already the case with SWM8s (which I assume require a BSF on each output in a MDU where two units share one SWM8)

 

I do not expect to see another SWM16 or SWM32 like product that combines multiple DSWM23s into a single unit. The only advantage they offer is density, and perhaps in the case of the SWM32, cascade support. A DSWM23 would already offer the density advantages of the SWM16/SWM32, so there's no need for a lower volume product that's even more dense.


SL5, PI-6S, SA-6AL 3xSWM16, 21 H20-100, 1 H20-600, 7 H24-700/AM21





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